1. Field of the Invention
The present invention is directed to a pipelined processor. Specifically, the present invention is directed to a pipelined processor having sequential processing instructions wherein at least some of the processing instructions conditionally use an operand.
2. Prior Art
A typical processor architecture may include a series of processing instructions where an instruction having an immediate data format can use one or more operands. Because immediate instructions can not specify all the operands they need, they use implied operands that are typically the result of the prior instruction. The typical implied operands are an "accumulator," a register usually located in the arithmetic unit of a processor, or a "top of stack," the last memory location used in a last in first out data memory mechanisms. In addition to an accumulator or top of stack a pipeline architecture has several pipeline latches or bus states that may contain useful data that could also be used as an implied operand.
Restricting an immediate instruction's second operand to be the outputs of the previous instruction or data supplied by a single pipeline latch limits the functionality of the immediate instruction in the processor. It is therefore an object of the present invention to provide a pipelined processor enhanced functionality through an expanded availability of operands that can be received by an immediate instruction.